IBIS Macromodel Task Group Meeting date: 23 June 2009 Members (asterisk for those attending): Adge Hawes, IBM Ambrish Varma, Cadence Design Systems Anders Ekholm, Ericsson * Arpad Muranyi, Mentor Graphics Corp. Barry Katz, SiSoft * Bob Ross, Teraspeed Consulting Group Brad Brim, Sigrity Brad Griffin, Cadence Design Systems Chris McGrath, Synopsys David Banas, Xilinx Deepak Ramaswany, Ansoft Donald Telian, consultant Doug White, Cisco Systems * Eckhard Lenski, Nokia-Siemens Networks Essaid Bensoudane, ST Microelectronics Fangyi Rao, Agilent Ganesh Narayanaswamy, ST Micro Gang Kang, Sigrity Hemant Shah, Cadence Design Systems Ian Dodd, Agilent Jerry Chuang, Xilinx Joe Abler, IBM * John Angulo, Mentor Graphics John Shields, Mentor Graphics Ken Willis, Cadence Design Systems Kumar Keshavan, Sigrity Lance Wang, Cadence Design Systems Luis Boluna, Cisco Systems Michael Mirmak, Intel Corp. * Mike LaBonte, Cisco Systems Mike Steinberger, SiSoft Mustansir Fanaswalla, Xilinx Patrick O'Halloran, Tiburon Design Automation Paul Fernando, NCSU Pavani Jella, TI * Radek Biernacki, Agilent (EESof) Randy Wolff, Micron Technology Ray Comeau, Cadence Design Systems Richard Mellitz, Intel Richard Ward, Texas Instruments Samuel Mertens, Ansoft Sam Chitwood, Sigrity Sanjeev Gupta, Agilent Shangli Wu, Cadence Design Systems Sid Singh, Extreme Networks Stephen Scearce, Cisco Systems Steve Pytel, Ansoft Syed Huq, Cisco Systems Syed Sadeghi, ST Micro Ted Mido, Synopsys Terry Jernberg, Cadence Design Systems Todd Westerhoff, SiSoft Vladimir Dmitriev-Zdorov Vikas Gupta, Xilinx Vuk Borich, Agilent * Walter Katz, SiSoft Zhen Mu, Cadence Design Systems ------------------------------------------------------------------------ Opens: Arpad: Should we add a suggestion for clock_times calculation algorithm to the IBIS-AMI specification? - Adding many clock time steps can accumulate significant error. - Walter: Tools need to have correct order of evaluation - Radek: Agree with Arpad - Walter: Floating point engines should be able to add a million million numbers before losing accuracy - Mike: A rational expression format may be more accurate - Arpad: We need to work with what we have - We want to prevent model makers from making simple mistakes up front AR: Arpad write a BIRD to clarify time period accuracy requirements -------------------------- Call for patent disclosure: - No one declared a patent. ------------- Review of ARs: - Todd: Write IBIS s-param BIRD - Still working on it - Arpad: Write parameter passing syntax proposal (BIRD draft) for *-AMS models in IBIS that is consistent with the parameter passing syntax of the AMI models - TBD - TBD: Propose a parameter passing syntax for the SPICE - [External ...] also? - TBD - Arpad: Review the documentation (annotation) in the macro libraries. - Deferred until a demand arises or we have nothing else to do ------------- New Discussion: User defined functions: - Arpad: These may be useful with complicated expressions - HSPICE definition does not look complicated - Walter: It is more complicated than it looks - This is for interconnect, with mostly computed numbers - Mike: Agree with Walter - These files should be machine generated, not hand crafted - Bob: This raises the bar for the required depth of HSPICE compatibility - Radek: Can expressions include voltages and times? - Walter: We are not allowing that - Arpad: It is evaluated before the simulation starts, not dynamically - Mike: It could be difficult for simulators without the capability - V and I can be known only after a DC solution - Arpad: Dynamic evaluation - Bob: These are introduced by single quotes - That is HSPICE-specific - We decided to not have user-defined functions Built-in functions: - Arpad: Will we have ternary operators? - Mike: Does that allow non-linearity? - Walter: These are evaluated before simulation - We should not have the ternary, but not if/else - Arpad: This will make it harder to switch on different corners - A single circuit could use conditionals to implement typ/min/max - Walter: The industry does not need this complication - Are interconnect model generator tools doing this today? - Arpad: Some customers are using parameters to select corner cases - Walter: For silicon yes, for interconnect no - Mike: It would be good to have the input of interconnect model generators - Walter: We can ask at DAC - Bob: We are not sure if there will be a presentation on this - Walter: I could create one - We will need Synopsys feedback - Will not put it one the web yet - We decided to not have if/else/endif or ternary operator Walter showed a "best practices" page: - Avoid scaling - Start all names with [a-zA-Z] - Arpad: We have a table spelling out more complex rules for this - Walter: These are recommended practices only - Do not mix numbers and alphas in node names - For example, 1A and 1B are the same node in HSPICE Walter showed the IBIS-IS document: - Many external references can be deleted - They mostly point to things that we don't need - Some refer to tables that are on the same page - Eliminating global parameters allows a lot of material to be deleted - Reference to page 96: Do we want to pull that material in? - The E element had some things that are really for the G element - These were moved to the G element Arpad: Will we keep the items we are dropping in the document for a while? - We will edit later after reading the minutes - Things like conditionals are already removed - Arpad: Walter could check if anything else needs to go - Walter: OK AR: Walter will send out the updated document Next meeting: 30 June 2009 12:00pm PT -------- IBIS Interconnect SPICE Wish List: 1) Simulator directives